Professor - Microsystems Engineering
Phone Number: +971 2 810 9214
Dr. Irfan Saadat received a BS degree in Electrical Engineering and BS in Computer Science from King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia in 1983, and MEng and PhD in Electrical Engineering from Cornell University, Ithaca, NY, in 1984 and 1990 respectively.
From 1990 to 1989, he worked with Fairchild Research Center, Santa Clara, CA, USA, which was part of National Semiconductor Corp. He worked on process integration covering Back of End Line (BEOL), Middle of line (MOL), Silicidation and Spin on Dielectrics. Then he went on to work on Systems on Chip process integration by developing an embedded DRAM on CMOS technology flow of 0.25um node, using stacked capacitor scheme. In 1990, Dr. Saadat moved to PDF Solutions, San Jose, CA, USA, a global leader in Semiconductor manufacturing consulting. Before joining Masdar Institute, Dr. Saadat was Senior Engagement Director and Technical Fellow with PDF Solutions.
He had been managing the PDF engagements with a leading US based microelectronics company starting from the 90nm node. For the last two years, Dr. Saadat was managing the 22/20nm CMOS project at a leading global semiconductor alliance. He also worked with various Alliance members in Europe and Asia in technology transfer and ramping. Dr. Saadat has authored and co-authored more than 9 publications in leading semiconductor conferences and journals; and has been granted 7 US patents.
- FDN 473
Advisor to Current Masdar Institute Students
- Marwa Attiya
- Omar Ali Amin Mohamed Alnemer
- Helmy Hafidh Aziz Ally
- Taryam Al Shamsi
- Aamna Rashed Alshehhi
- Khaled Salem Ali S. Alnuaimi
Research Interest/Research Projects
- Design and Process Interaction challenges for 28nm, 20nm node and beyond. The key area of focus is the optimization technology complexity, design complexity/cost, and shrink factor from prior nodes.
- Manufacturability assessment of developing technology. This includes assessment of key elements of new technology in R&D and evaluation of their strength/weakness in technology transfer and ramp.
- Enablement of early designs on a given node: The assessment of sweet spot of design/process through characterization of the process and design space.
- 20nm process integration challenges for silicides, MOL, BEOL and 3D packaging.
- Research projects:
- Characterization of 28nm and 20nm technology for manufacturability and design. Focus on local layout effect vs. PDK and design rule space.
- Reliability assessment BEOL, MOL for 28nm and 20nm
- Thin film transistor using low temperature processing
- Low resistance contacts and vias using carbon nano-tubes
- Yield Improvement Using a Fast Product Wafer Level Monitoring System; K. Hess, C.; Saadat, I, et al. Advanced Semiconductor Manufacturing Conference, 2006. ASMC 2006. The 17th Annual SEMI/IEEE Meeting, May 22-24, 2006 Page(s):417 - 422
- CoSi2 integrated fuses on poly silicon for low voltage 0.18 μm CMOS applications; Kalnitsky, A.; Saadat, I Electron Devices Meeting, 1999. IEDM Technical Digest. International, 5-8 Dec. 1999 Page(s):765 - 768
- VLSI multilevel micro-coaxial interconnects for high speed devices; Thomas, M.E.; Saadat, I.A.; Sekigahama, S.; International Electron Devices Meeting, 1990. Technical Digest., l9-12 Dec. 1990 Page(s):55 - 58