Faculty

Faculty

Hasan Munir Nayfeh

Hasan Munir Nayfeh

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Associate Professor - Microsystems Engineering
 
 
Dr. Hasan M. Nayfeh received his Ph.D. (2003) in Electrical Engineering in the area of strained silicon/SiGe devices from MIT (Cambridge, MA). After joining IBM Semiconductor Research & Development Center (Hopewell Junction, NY) in 2003, he worked on SOI device design that resulted in the successful deployment of 65nm and 45nm technology nodes.
 
From 2010-2011 his focus was on technology definition for the 22nm node in his role as lead device design senior engineer. He has 30 technical publications, 4 issued patents, and is a Senior Member of the IEEE.
Research Interests / Research Projects:
Dr. Hasan M. Nayfeh’s research group scope is in design, fabrication, characterization, and modeling device and building block circuits in support of microsystems.
Selected Publications:
  • H. M. Nayfeh, N. Rovedo, A. Bryant, S. Narasimha, A. Kumar, X. Yu, Y. Lee, A. Kumar, J. Sleight,  R. Robison, N. Su, J. Yu, W. Rausch, H. Mallela, G. Freeman, “ Impact of Asymmetric Doping on Nanoscale  n-type MOSFETs and Circuit Performance”,  IEEE Transactions on Electron Devices,  December. 2009.
  •  H. M. Nayfeh, S. Jeng, S. Narasimha, S. Butt, R. Pal, A. Waite, K. Tabakman, J. B. Johnson, J. Liu, J. Holt, T. Adam, A. Madan, A. Domenicucci, "Hole Transport in Nanoscale p-type MOSFET SOI Devices with High Strain" 2007 IEEE Device Research Conference, June 21-23, 2007, University of Notre Dame South Bend, Indiana.
  •  S. Narasimha, K. Onishi, H. M. Nayfeh, et al..   “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography”, 2006 IEEE Electron Devices Meeting.
 
See here for full list: web: http://alum.mit.edu/www/hnayfeh